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<!@TC:1732004095>
#Build: Synplify Pro (R) V-2023.09L-2, Build 349R, Sep 17 2024
#install: C:\ToolSoftware\Diamond\3.14\synpbase
#OS: Windows 10 or later
#Hostname: DESKTOP-LK1D0PP

# Tue Nov 19 16:14:55 2024

#Implementation: MXO2_2000HC


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1732004097> | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=compilerReport2></a>Synopsys VHDL Compiler, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1732004097> | Running in 64-bit mode 
@N: : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:44:7:44:10:@N::@XP_MSG">CL202_MXO2-2000HC_Top.vhd(44)</a><!@TM:1732004097> | Top entity is set to Top.
File D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd changed - recompiling
@N:<a href="@N:CD140:@XP_HELP">CD140</a> : <!@TM:1732004097> | Using the VHDL 1993 Standard for file 'C:\ToolSoftware\Diamond\3.14\cae_library\synthesis\vhdl\machxo2.vhd'. 
@N:<a href="@N:CD140:@XP_HELP">CD140</a> : <!@TM:1732004097> | Using the VHDL 1993 Standard for file 'D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd'. 
VHDL syntax check successful!
File D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:44:7:44:10:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(44)</a><!@TM:1732004097> | Synthesizing work.top.top_arch.
<font color=#A52A2A>@W:<a href="@W:CD326:@XP_HELP">CD326</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:363:1:363:3:@W:CD326:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(363)</a><!@TM:1732004097> | Port pulseout_48 of entity work.laserpulse is unconnected. If a port needs to remain unconnected, use the keyword open.</font>
<font color=#A52A2A>@W:<a href="@W:CD326:@XP_HELP">CD326</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:363:1:363:3:@W:CD326:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(363)</a><!@TM:1732004097> | Port pulseout_49 of entity work.laserpulse is unconnected. If a port needs to remain unconnected, use the keyword open.</font>
<font color=#A52A2A>@W:<a href="@W:CG296:@XP_HELP">CG296</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:474:1:474:8:@W:CG296:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(474)</a><!@TM:1732004097> | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:478:55:478:58:@W:CG290:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(478)</a><!@TM:1732004097> | Referenced variable clr is not in sensitivity list.</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:478:30:478:45:@W:CG290:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(478)</a><!@TM:1732004097> | Referenced variable reset1553_check is not in sensitivity list.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:126:7:126:14:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(126)</a><!@TM:1732004097> | Signal key_clk is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:130:7:130:13:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(130)</a><!@TM:1732004097> | Signal key_up is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:131:7:131:15:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(131)</a><!@TM:1732004097> | Signal key_down is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:132:7:132:13:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(132)</a><!@TM:1732004097> | Signal key_ok is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:133:7:133:17:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(133)</a><!@TM:1732004097> | Signal key_cancel is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:134:7:134:16:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(134)</a><!@TM:1732004097> | Signal key_laser is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:135:7:135:16:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(135)</a><!@TM:1732004097> | Signal key_cross is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:136:7:136:17:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(136)</a><!@TM:1732004097> | Signal key1_count is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:137:7:137:17:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(137)</a><!@TM:1732004097> | Signal key2_count is undriven. Either assign the signal a value or remove the signal declaration.</font>
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:142:7:142:13:@W:CD638:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(142)</a><!@TM:1732004097> | Signal reg_oe is undriven. Either assign the signal a value or remove the signal declaration.</font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:682:7:682:21:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(682)</a><!@TM:1732004097> | Synthesizing work.xwj_laser_trig.xlt_arch.
Post processing for work.xwj_laser_trig.xlt_arch
Running optimization stage 1 on xwj_laser_trig .......
Finished optimization stage 1 on xwj_laser_trig (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:724:7:724:27:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(724)</a><!@TM:1732004097> | Synthesizing work.pulsedelaytrig_async.pdta_arch.
<font color=#A52A2A>@W:<a href="@W:CG296:@XP_HELP">CG296</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:740:1:740:8:@W:CG296:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(740)</a><!@TM:1732004097> | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:745:16:745:24:@W:CG290:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(745)</a><!@TM:1732004097> | Referenced variable setdelay is not in sensitivity list.</font>
<font color=#A52A2A>@W:<a href="@W:CG290:@XP_HELP">CG290</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:744:16:744:24:@W:CG290:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(744)</a><!@TM:1732004097> | Referenced variable setwidth is not in sensitivity list.</font>
Post processing for work.pulsedelaytrig_async.pdta_arch
Running optimization stage 1 on PulseDelayTrig_async .......
<font color=#A52A2A>@W:<a href="@W:CL117:@XP_HELP">CL117</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:742:2:742:4:@W:CL117:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(742)</a><!@TM:1732004097> | Latch generated from process for signal count_set(15 downto 0); possible missing assignment in an if or case statement.</font>
<font color=#A52A2A>@W:<a href="@W:CL117:@XP_HELP">CL117</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:742:2:742:4:@W:CL117:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(742)</a><!@TM:1732004097> | Latch generated from process for signal Delay_set(15 downto 0); possible missing assignment in an if or case statement.</font>
Finished optimization stage 1 on PulseDelayTrig_async (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 94MB)
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:646:7:646:22:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(646)</a><!@TM:1732004097> | Synthesizing work.tb_delayprocess.tb_delayprocess_arch.
Post processing for work.tb_delayprocess.tb_delayprocess_arch
Running optimization stage 1 on TB_DelayProcess .......
Finished optimization stage 1 on TB_DelayProcess (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:546:7:546:17:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(546)</a><!@TM:1732004097> | Synthesizing work.laserpulse.laserpulse_arch.
Post processing for work.laserpulse.laserpulse_arch
Running optimization stage 1 on LaserPulse .......
<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:558:2:558:13:@W:CL240:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(558)</a><!@TM:1732004097> | Signal PulseOut_49 is floating; a simulation mismatch is possible.</font>
<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:557:8:557:19:@W:CL240:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(557)</a><!@TM:1732004097> | Signal PulseOut_48 is floating; a simulation mismatch is possible.</font>
Finished optimization stage 1 on LaserPulse (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB)
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:510:7:510:15:@N:CD630:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(510)</a><!@TM:1732004097> | Synthesizing work.nonshake.nonshake_arch.
Post processing for work.nonshake.nonshake_arch
Running optimization stage 1 on NonShake .......
Finished optimization stage 1 on NonShake (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB)
Post processing for work.top.top_arch
Running optimization stage 1 on Top .......
<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:87:2:87:5:@W:CL240:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(87)</a><!@TM:1732004097> | Signal TX6 is floating; a simulation mismatch is possible.</font>
<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:85:2:85:5:@W:CL240:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(85)</a><!@TM:1732004097> | Signal TX4 is floating; a simulation mismatch is possible.</font>
<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:81:2:81:5:@W:CL240:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(81)</a><!@TM:1732004097> | Signal TX2 is floating; a simulation mismatch is possible.</font>
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:148:7:148:14:@N:CL134:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(148)</a><!@TM:1732004097> | Found RAM reg_mem, depth=8, width=16
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:152:7:152:16:@W:CL271:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(152)</a><!@TM:1732004097> | Pruning unused bits 7 to 3 of reg_mem_0(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:152:7:152:16:@W:CL271:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(152)</a><!@TM:1732004097> | Pruning unused bits 15 to 8 of reg_mem_2(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL117:@XP_HELP">CL117</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:476:2:476:4:@W:CL117:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(476)</a><!@TM:1732004097> | Latch generated from process for signal SPulse_Check; possible missing assignment in an if or case statement.</font>
Finished optimization stage 1 on Top (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Running optimization stage 2 on NonShake .......
Finished optimization stage 2 on NonShake (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 96MB)
Running optimization stage 2 on LaserPulse .......
Finished optimization stage 2 on LaserPulse (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Running optimization stage 2 on TB_DelayProcess .......
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:660:2:660:4:@N:CL189:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(660)</a><!@TM:1732004097> | Register bit Clk_Count(7) is always 0.
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:660:2:660:4:@W:CL260:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(660)</a><!@TM:1732004097> | Pruning register bit 7 of Clk_Count(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
Finished optimization stage 2 on TB_DelayProcess (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Running optimization stage 2 on PulseDelayTrig_async .......
Finished optimization stage 2 on PulseDelayTrig_async (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Running optimization stage 2 on xwj_laser_trig .......
Finished optimization stage 2 on xwj_laser_trig (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB)
Running optimization stage 2 on Top .......
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:66:2:66:10:@N:CL159:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(66)</a><!@TM:1732004097> | Input FSMC_CLK is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:70:2:70:12:@N:CL159:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(70)</a><!@TM:1732004097> | Input FSMC_NWAIT is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:80:2:80:5:@N:CL159:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(80)</a><!@TM:1732004097> | Input RX2 is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:84:2:84:5:@N:CL159:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(84)</a><!@TM:1732004097> | Input RX4 is unused.
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\CL202_MXO2-2000HC_Top.vhd:86:2:86:5:@N:CL159:@XP_MSG">CL202_MXO2-2000HC_Top.vhd(86)</a><!@TM:1732004097> | Input RX6 is unused.
Finished optimization stage 2 on Top (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB)

For a summary of runtime per design unit, please see file:
==========================================================
Linked File:  <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\layer0.duruntime:@XP_FILE">layer0.duruntime</a>



At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 19 16:14:57 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1732004097> | Running in 64-bit mode 
File D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 19 16:14:57 2024

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_comp.rt.csv:@XP_FILE">CL202_MXO2_2000HC_comp.rt.csv</a>

@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 22MB peak: 23MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 19 16:14:57 2024

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1732004095>
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=compilerReport9></a>Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1732004098> | Running in 64-bit mode 
File D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Tue Nov 19 16:14:58 2024

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1732004095>
# Tue Nov 19 16:14:58 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=mapperReport15></a>Synopsys Lattice Technology Pre-mapping, Version map202309lat, Build 191R, Built Sep 17 2024 10:38:50, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 197MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1732004100> | No constraint file specified. 
Linked File:  <a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC_scck.rpt:@XP_FILE">CL202_MXO2_2000HC_scck.rpt</a>
See clock summary report "D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC_scck.rpt"
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1732004100> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1732004100> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1732004100> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 197MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 197MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 203MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 203MB peak: 205MB)

NConnInternalConnection caching is on
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004100> | Applying initial value "000000000000000000000000" on instance LockData[23:0]. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1732004100> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 255MB peak: 255MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 255MB peak: 255MB)

<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[1] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[2] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[4] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[5] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[7] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[8] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[9] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[10] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[11] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[12] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[13] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[14] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.count_set[15] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[1] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[2] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[4] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[5] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[7] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[8] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[9] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[10] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[11] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[12] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[13] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[14] is reduced to a combinational gate by constant propagation.</font>
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:MO129:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004100> | Sequential instance U7.Delay_set[15] is reduced to a combinational gate by constant propagation.</font>

Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 255MB peak: 255MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 255MB peak: 256MB)


Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 257MB peak: 257MB)


mixed edge conversion for GCC is OFF
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1732004100> | Incompatible asynchronous control logic preventing generated clock conversion. 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1732004100> | GCC encountered Inferred Clock constraint on net GCC considers to be data U3.Clk_10ms[17]; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1732004100> | GCC encountered Inferred Clock constraint on net GCC considers to be data U3.PulseOut; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1732004100> | GCC encountered Inferred Clock constraint on net GCC considers to be data Clk_Count[16]; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1732004100> | GCC encountered Inferred Clock constraint on net GCC considers to be data Clk_Count[13]; this will likely lead to failure to convert</font> 

Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 257MB peak: 258MB)

<font color=#A52A2A>@W:<a href="@W:BZ101:@XP_HELP">BZ101</a> : <!@TM:1732004100> | Potential glitch can occur at the output of 2 instances  </font> 

Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 258MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 258MB)

@N:<a href="@N:FX1184:@XP_HELP">FX1184</a> : <!@TM:1732004100> | Applying syn_allowed_resources blockrams=7 on top level netlist Top  

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 258MB)



<a name=mapperReport16></a>Clock Summary</a>
******************

          Start                                       Requested     Requested     Clock                      Clock          Clock
Level     Clock                                       Frequency     Period        Type                       Group          Load 
---------------------------------------------------------------------------------------------------------------------------------
0 -       Top|Clk                                     100.0 MHz     10.000        inferred                   (multiple)     256  
1 .         Top|Clk_Count_derived_clock[13]           100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     16   
1 .         LaserPulse|Clk_10ms_derived_clock[17]     100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     9    
1 .         Top|Clk_Count_derived_clock[16]           100.0 MHz     10.000        derived (from Top|Clk)     (multiple)     9    
                                                                                                                                 
0 -       Top|FSMC_NWE                                100.0 MHz     10.000        inferred                   (multiple)     131  
                                                                                                                                 
0 -       Top|FSMC_NADV                               100.0 MHz     10.000        inferred                   (multiple)     16   
                                                                                                                                 
0 -       LaserPulse|PulseOut_inferred_clock          100.0 MHz     10.000        inferred                   (multiple)     0    
=================================================================================================================================



Clock Load Summary
***********************

                                          Clock     Source                             Clock Pin              Non-clock Pin            Non-clock Pin   
Clock                                     Load      Pin                                Seq Example            Seq Example              Comb Example    
-------------------------------------------------------------------------------------------------------------------------------------------------------
Top|Clk                                   256       Clk(port)                          Clr_Count[22:0].C      -                        -               
Top|Clk_Count_derived_clock[13]           16        Clk_Count[16:0].Q[13](dff)         U2.Count[7:0].C        -                        -               
LaserPulse|Clk_10ms_derived_clock[17]     9         U3.Clk_10ms[17:0].Q[17](sdffr)     U3.Stop_sig.C          -                        -               
Top|Clk_Count_derived_clock[16]           9         Clk_Count[16:0].Q[16](dff)         TB_watchdog[8:0].C     -                        -               
                                                                                                                                                       
Top|FSMC_NWE                              131       FSMC_NWE(port)                     reg_mem[15:0].CLK      -                        -               
                                                                                                                                                       
Top|FSMC_NADV                             16        FSMC_NADV(port)                    FSMC_Add[15:0].C       -                        -               
                                                                                                                                                       
LaserPulse|PulseOut_inferred_clock        0         U3.PulseOut.OUT(and)               -                      U5.Delay_set[15:0].E     TB_sig.B[0](mux)
=======================================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT531:@XP_HELP">MT531</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:412:2:412:4:@W:MT531:@XP_MSG">cl202_mxo2-2000hc_top.vhd(412)</a><!@TM:1732004100> | Found signal identified as System clock which controls 17 sequential elements including SPulseCount[15:0].  Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:660:2:660:4:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(660)</a><!@TM:1732004100> | Found inferred clock Top|Clk which controls 256 sequential elements including U4.Clk_Count[6:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:152:7:152:16:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(152)</a><!@TM:1732004100> | Found inferred clock Top|FSMC_NWE which controls 131 sequential elements including reg_mem_7[15:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:283:2:283:4:@W:MT529:@XP_MSG">cl202_mxo2-2000hc_top.vhd(283)</a><!@TM:1732004100> | Found inferred clock Top|FSMC_NADV which controls 16 sequential elements including FSMC_Add[15:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport17></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

4 non-gated/non-generated clock tree(s) driving 394 clock pin(s) of sequential element(s)
4 gated/generated clock tree(s) driving 51 clock pin(s) of sequential element(s)
0 instances converted, 51 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk@|E:Clk_Count[16:0]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       Clk                 port                   256        Clk_Count[16:0]
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:PulseOutCheck@|E:U7.Delay_set[6]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       PulseOutCheck       port                   6          U7.Delay_set[6]
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:FSMC_NADV@|E:FSMC_Add[15:0]@|F:@syn_dgcc_clockid0_7==1@|M:ClockId_0_7 @XP_NAMES_BY_PROP">ClockId_0_7</a>       FSMC_NADV           port                   16         FSMC_Add[15:0] 
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:FSMC_NWE@|E:reg_mem_7[15:0]@|F:@syn_dgcc_clockid0_8==1@|M:ClockId_0_8 @XP_NAMES_BY_PROP">ClockId_0_8</a>       FSMC_NWE            port                   116        reg_mem_7[15:0]
=======================================================================================
================================================================== Gated/Generated Clocks ===================================================================
Clock Tree ID     Driving Element             Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
-------------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:U3.Clk_10ms[17:0].Q[17]@|E:U3.Count_stop[7:0]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       U3.Clk_10ms[17:0].Q[17]     sdffr                  9                      U3.Count_stop[7:0]     Derived clock on input (not legal for GCC)
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk_Count[16:0].Q[13]@|E:U2.Count[7:0]@|F:@syn_dgcc_clockid0_4==1@|M:ClockId_0_4 @XP_NAMES_BY_PROP">ClockId_0_4</a>       Clk_Count[16:0].Q[13]       dff                    16                     U2.Count[7:0]          Derived clock on input (not legal for GCC)
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:U3.PulseOut.OUT@|E:SPulseCount[15:0]@|F:@syn_dgcc_clockid0_6==1@|M:ClockId_0_6 @XP_NAMES_BY_PROP">ClockId_0_6</a>       U3.PulseOut.OUT             and                    17                     SPulseCount[15:0]      Clock source is invalid for GCC           
<a href="@|L:D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_prem.srm@|S:Clk_Count[16:0].Q[16]@|E:TB_watchdog[8:0]@|F:@syn_dgcc_clockid0_9==1@|M:ClockId_0_9 @XP_NAMES_BY_PROP">ClockId_0_9</a>       Clk_Count[16:0].Q[16]       dff                    9                      TB_watchdog[8:0]       Derived clock on input (not legal for GCC)
=============================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1732004100> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 258MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 259MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 259MB peak: 259MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 174MB peak: 260MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 19 16:15:00 2024

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1732004095>
# Tue Nov 19 16:15:00 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC
<a name=mapperReport23></a>Synopsys Lattice Technology Mapper, Version map202309lat, Build 191R, Built Sep 17 2024 10:38:50, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1732004104> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1732004104> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1732004104> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 198MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 198MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 202MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 253MB peak: 253MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Removing sequential instance U7.Delay_set[6] because it is equivalent to instance U7.Delay_set[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Removing sequential instance U7.Delay_set[3] because it is equivalent to instance U7.Delay_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Removing sequential instance U7.count_set[6] because it is equivalent to instance U7.Delay_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Removing sequential instance U7.count_set[3] because it is equivalent to instance U7.Delay_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Removing sequential instance U7.count_set[0] because it is equivalent to instance U7.Delay_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Removing sequential instance U8.count_set[6] because it is equivalent to instance U8.count_set[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Removing sequential instance U8.count_set[3] because it is equivalent to instance U8.count_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[0] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[1] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[2] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[3] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[4] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[5] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[6] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[7] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[8] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[9] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[10] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[11] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[12] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[13] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[14] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net FSMC_AD[15] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net Clk_Count[13] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net LaserPulse_Sig has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net Clk_Count[16] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.Clk_10ms[17] has multiple drivers .</font>

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 258MB peak: 258MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Removing instance U6.count_set[3] because it is equivalent to instance U6.count_set[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Removing instance U6.count_set[2] because it is equivalent to instance U6.count_set[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@W:BN132:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Removing instance U6.count_set[1] because it is equivalent to instance U6.count_set[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:619:2:619:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(619)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance U3.Count_stop[7:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:412:2:412:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(412)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance SPulseCount[15:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:313:2:313:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(313)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance Clk_Count[16:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:394:2:394:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(394)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance TB_watchdog[8:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:245:2:245:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(245)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance Clr_Count[22:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:742:2:742:4:@N:MO231:@XP_MSG">cl202_mxo2-2000hc_top.vhd(742)</a><!@TM:1732004104> | Found counter in view:work.Top(top_arch) instance U7.count[15:0] 
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_89 has multiple drivers .</font>
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance U7.Delay_set[0]. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1732004104> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[3]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[4]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[5]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[6]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[7]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[8]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[9]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[10]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[11]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[12]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[13]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[14]. 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1732004104> | Applying initial value "0" on instance FSMC_Add[15]. 
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_530 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_532 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_533 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_534 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_536 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_538 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_539 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_540 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_541 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_542 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_543 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net N_545 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U7.un8_count_0 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U7.un8_count_1 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U7.un8_count_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_0 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_1 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_3 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_4 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_5 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_6 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_7 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_8 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_9 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_10 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_11 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_12 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_13 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_14 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_15 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_16 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_17 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_18 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_19 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_20 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_21 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_22 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_23 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_0 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_1 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_3 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_4 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_5 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_6 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_7 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_8 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_9 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_10 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_11 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_12 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_13 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_14 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un12_count_15 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un1_clk_10mslto17 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.un1_clk_10mslto14 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_0 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_1 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_3 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_4 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_5 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_6 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U3.count_stop_7 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_0 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_1 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_3 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_4 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_5 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_6 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_7 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_8 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_9 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_10 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_11 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_12 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:44:7:44:10:@W:BN161:@XP_MSG">cl202_mxo2-2000hc_top.vhd(44)</a><!@TM:1732004104> | Net U8.count_1_13 has multiple drivers .</font>

Only the first 100 messages of id 'BN161' are reported. To see all messages use 'report_messages -log D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synlog\CL202_MXO2_2000HC_fpga_mapper.srr -id BN161' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN161} -count unlimited' in the Tcl shell.

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 261MB peak: 261MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 261MB peak: 262MB)


Available hyper_sources - for debug and ip models
	None Found

NConnInternalConnection caching is on

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 261MB peak: 262MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 262MB peak: 262MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 262MB peak: 263MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 262MB peak: 263MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 263MB peak: 263MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 264MB peak: 264MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     0.95ns		 119 /       433
   2		0h:00m:00s		     0.95ns		 119 /       433

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 264MB peak: 265MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1732004104> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
<font color=#A52A2A>@W:<a href="@W:MO129:@XP_HELP">MO129</a> : <!@TM:1732004104> | Sequential instance U7.Delay_set[0] is reduced to a combinational gate by constant propagation.</font> 
@N:<a href="@N:FO126:@XP_HELP">FO126</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:148:7:148:14:@N:FO126:@XP_MSG">cl202_mxo2-2000hc_top.vhd(148)</a><!@TM:1732004104> | Generating RAM reg_mem[15:0]
@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@A:BN291:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Boundary register U5.Q.fb (in view: work.Top(top_arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:700:2:700:4:@A:BN291:@XP_MSG">cl202_mxo2-2000hc_top.vhd(700)</a><!@TM:1732004104> | Boundary register U8.Q.fb (in view: work.Top(top_arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:580:2:580:4:@A:BN291:@XP_MSG">cl202_mxo2-2000hc_top.vhd(580)</a><!@TM:1732004104> | Boundary register U3.Pulse_Sig.fb (in view: work.Top(top_arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
@A:<a href="@A:BN291:@XP_HELP">BN291</a> : <a href="d:\light_source\cpld\cl202_b(i232o232-202107231608)\cl202_mxo2-2000hc_top.vhd:580:2:580:4:@A:BN291:@XP_MSG">cl202_mxo2-2000hc_top.vhd(580)</a><!@TM:1732004104> | Boundary register U3.Half_Width.fb (in view: work.Top(top_arch)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 265MB peak: 265MB)


Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 265MB peak: 266MB)


Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 265MB peak: 266MB)


Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 209MB peak: 266MB)

Writing Analyst data base D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\synwork\CL202_MXO2_2000HC_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 265MB peak: 266MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1732004104> | Writing EDF file: D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.edi 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1732004104> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 273MB peak: 273MB)


Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 273MB peak: 274MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 271MB peak: 274MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1732004104> | Found inferred clock Top|Clk with period 10.00ns. Please declare a user-defined clock on port Clk.</font> 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1732004104> | Found inferred clock Top|FSMC_NWE with period 10.00ns. Please declare a user-defined clock on port FSMC_NWE.</font> 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1732004104> | Found inferred clock Top|FSMC_NADV with period 10.00ns. Please declare a user-defined clock on port FSMC_NADV.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1732004104> | Found clock Top|Clk_Count_derived_clock[13] with period 10.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1732004104> | Found clock Top|Clk_Count_derived_clock[16] with period 10.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1732004104> | Found clock LaserPulse|Clk_10ms_derived_clock[17] with period 10.00ns  
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1732004104> | Found inferred clock LaserPulse|PulseOut_inferred_clock with period 10.00ns. Please declare a user-defined clock on net U3.LaserPulse_Sig.</font> 


<a name=timingReport24></a>##### START OF TIMING REPORT #####[</a>
# Timing report written on Tue Nov 19 16:15:03 2024
#


Top view:               Top
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1732004104> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1732004104> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary25></a>Performance Summary</a>
*******************


Worst slack in design: 0.378

                                          Requested     Estimated     Requested     Estimated                Clock                      Clock          
Starting Clock                            Frequency     Frequency     Period        Period        Slack      Type                       Group          
-------------------------------------------------------------------------------------------------------------------------------------------------------
LaserPulse|Clk_10ms_derived_clock[17]     100.0 MHz     249.7 MHz     10.000        4.004         5.996      derived (from Top|Clk)     (multiple)     
LaserPulse|PulseOut_inferred_clock        100.0 MHz     NA            10.000        NA            NA         inferred                   (multiple)     
Top|Clk                                   100.0 MHz     103.9 MHz     10.000        9.622         0.378      inferred                   (multiple)     
Top|Clk_Count_derived_clock[13]           100.0 MHz     377.1 MHz     10.000        2.652         14.697     derived (from Top|Clk)     (multiple)     
Top|Clk_Count_derived_clock[16]           100.0 MHz     204.6 MHz     10.000        4.887         6.949      derived (from Top|Clk)     (multiple)     
Top|FSMC_NADV                             100.0 MHz     151.2 MHz     10.000        6.615         3.385      inferred                   (multiple)     
Top|FSMC_NWE                              100.0 MHz     165.7 MHz     10.000        6.035         3.965      inferred                   (multiple)     
System                                    100.0 MHz     169.4 MHz     10.000        5.904         4.096      system                     system_clkgroup
=======================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





<a name=clockRelationships26></a>Clock Relationships</a>
*******************

Clocks                                                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                               Ending                                 |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                 System                                 |  10.000      4.096   |  No paths    -      |  No paths    -      |  No paths    -    
System                                 Top|Clk                                |  10.000      6.068   |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk                                Top|Clk                                |  10.000      0.378   |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk                                Top|FSMC_NWE                           |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk                                Top|FSMC_NADV                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk                                Top|Clk_Count_derived_clock[16]        |  10.000      5.113   |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NWE                           System                                 |  10.000      4.168   |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NWE                           Top|Clk                                |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NWE                           Top|FSMC_NWE                           |  10.000      3.965   |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NWE                           Top|FSMC_NADV                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NWE                           LaserPulse|Clk_10ms_derived_clock[17]  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NADV                          Top|FSMC_NWE                           |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|FSMC_NADV                          Top|FSMC_NADV                          |  10.000      3.385   |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[13]        Top|FSMC_NWE                           |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[13]        Top|FSMC_NADV                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[13]        Top|Clk_Count_derived_clock[13]        |  10.000      14.697  |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[16]        Top|Clk                                |  10.000      6.949   |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[16]        Top|FSMC_NWE                           |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[16]        Top|FSMC_NADV                          |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
Top|Clk_Count_derived_clock[16]        Top|Clk_Count_derived_clock[16]        |  10.000      15.401  |  No paths    -      |  No paths    -      |  No paths    -    
LaserPulse|Clk_10ms_derived_clock[17]  Top|Clk                                |  10.000      5.996   |  No paths    -      |  No paths    -      |  No paths    -    
LaserPulse|Clk_10ms_derived_clock[17]  LaserPulse|Clk_10ms_derived_clock[17]  |  10.000      14.505  |  No paths    -      |  No paths    -      |  No paths    -    
=====================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo27></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport28></a>Detailed Report for Clock: LaserPulse|Clk_10ms_derived_clock[17]</a>
====================================



<a name=startingSlack29></a>Starting Points with Worst Slack</a>
********************************

                     Starting                                                                        Arrival           
Instance             Reference                                 Type        Pin     Net               Time        Slack 
                     Clock                                                                                             
-----------------------------------------------------------------------------------------------------------------------
U3.Stop_sig          LaserPulse|Clk_10ms_derived_clock[17]     FD1S3DX     Q       LED_c[0]          1.044       5.996 
U3.Count_stop[0]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[0]     1.044       14.505
U3.Count_stop[1]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[1]     1.044       14.648
U3.Count_stop[2]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[2]     1.044       14.648
U3.Count_stop[3]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[3]     1.044       14.790
U3.Count_stop[4]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[4]     1.044       14.790
U3.Count_stop[5]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[5]     1.044       14.933
U3.Count_stop[6]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[6]     1.044       14.933
U3.Count_stop[7]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     Q       Count_stop[7]     1.044       16.817
=======================================================================================================================


<a name=endingSlack30></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                                          Required           
Instance             Reference                                 Type        Pin     Net                 Time         Slack 
                     Clock                                                                                                
--------------------------------------------------------------------------------------------------------------------------
U3.Stop_sig          LaserPulse|Clk_10ms_derived_clock[17]     FD1S3DX     D       count_stop_i        19.894       14.505
U3.Count_stop[0]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[1]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[2]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[3]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[4]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[5]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[6]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[7]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     SP      count_stop          19.528       14.707
U3.Count_stop[7]     LaserPulse|Clk_10ms_derived_clock[17]     FD1P3DX     D       Count_stop_s[7]     19.894       15.329
==========================================================================================================================



<a name=worstPaths31></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:73040:73796:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      3.533
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 5.996

    Number of logic level(s):                2
    Starting point:                          U3.Stop_sig / Q
    Ending point:                            U5.Delay_set[0] / SP
    The start point is clocked by            LaserPulse|Clk_10ms_derived_clock[17] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    The end   point is clocked by            Top|Clk [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
U3.Stop_sig         FD1S3DX      Q        Out     1.044     1.044 r     -         
LED_c[0]            Net          -        -       -         -           2         
U3.PulseOut         ORCALUT4     A        In      0.000     1.044 r     -         
U3.PulseOut         ORCALUT4     Z        Out     1.089     2.133 r     -         
PulseOut_i_buf      Net          -        -       -         -           2         
TB_sig              ORCALUT4     B        In      0.000     2.133 r     -         
TB_sig              ORCALUT4     Z        Out     1.400     3.533 r     -         
PulseOut_c[0]       Net          -        -       -         -           51        
U5.Delay_set[0]     FD1P3AX      SP       In      0.000     3.533 r     -         
==================================================================================




====================================
<a name=clockReport32></a>Detailed Report for Clock: Top|Clk</a>
====================================



<a name=startingSlack33></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                          Arrival          
Instance            Reference     Type        Pin     Net             Time        Slack
                    Clock                                                              
---------------------------------------------------------------------------------------
U6.count_set[0]     Top|Clk       FD1S3AX     Q       un9_count_0     1.188       0.378
U8.count_set[0]     Top|Clk       FD1S3AX     Q       un9_count_0     1.180       0.386
U5.Delay_set[0]     Top|Clk       FD1P3AX     Q       count_1_0       1.108       0.458
U8.Delay_set[0]     Top|Clk       FD1P3AX     Q       count_1_0       1.108       0.458
U6.Delay_set[0]     Top|Clk       FD1P3AX     Q       count_1_0       1.108       0.458
U5.count_set[0]     Top|Clk       FD1P3AX     Q       un9_count_0     1.044       0.522
U6.count[0]         Top|Clk       FD1S3IX     Q       count[0]        1.108       0.528
U5.count[0]         Top|Clk       FD1S3IX     Q       count[0]        1.108       0.528
U8.count[0]         Top|Clk       FD1S3IX     Q       count[0]        1.108       0.528
U5.Delay_set[1]     Top|Clk       FD1P3AX     Q       count_1_1       1.044       0.664
=======================================================================================


<a name=endingSlack34></a>Ending Points with Worst Slack</a>
******************************

                 Starting                                                       Required          
Instance         Reference     Type        Pin     Net                          Time         Slack
                 Clock                                                                            
--------------------------------------------------------------------------------------------------
U6.count[15]     Top|Clk       FD1S3IX     D       un11_count_s_33_0_S0_0       9.894        0.378
U8.count[15]     Top|Clk       FD1S3IX     D       un11_count_s_33_0_S0_1       9.894        0.386
U5.count[15]     Top|Clk       FD1S3IX     D       un11_count_s_33_0_S0         9.894        0.458
U6.count[13]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S0_0     9.894        0.520
U6.count[14]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S1_0     9.894        0.520
U8.count[13]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S0_1     9.894        0.528
U8.count[14]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S1_1     9.894        0.528
U5.count[13]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S0       9.894        0.600
U5.count[14]     Top|Clk       FD1S3IX     D       un11_count_cry_31_0_S1       9.894        0.600
U6.count[11]     Top|Clk       FD1S3IX     D       un11_count_cry_29_0_S0_0     9.894        0.663
==================================================================================================



<a name=worstPaths35></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:78135:83535:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      9.517
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     0.378

    Number of logic level(s):                19
    Starting point:                          U6.count_set[0] / Q
    Ending point:                            U6.count[15] / D
    The start point is clocked by            Top|Clk [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    The end   point is clocked by            Top|Clk [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
U6.count_set[0]            FD1S3AX     Q        Out     1.188     1.188 r     -         
un9_count_0                Net         -        -       -         -           6         
U6.un9_count_0_cry_0_0     CCU2D       A1       In      0.000     1.188 r     -         
U6.un9_count_0_cry_0_0     CCU2D       COUT     Out     1.544     2.732 r     -         
un9_count_0_cry_0          Net         -        -       -         -           1         
U6.un9_count_0_cry_1_0     CCU2D       CIN      In      0.000     2.732 r     -         
U6.un9_count_0_cry_1_0     CCU2D       S1       Out     1.549     4.281 r     -         
un9_count_n[2]             Net         -        -       -         -           1         
U6.un11_count_cry_1_0      CCU2D       A1       In      0.000     4.281 r     -         
U6.un11_count_cry_1_0      CCU2D       COUT     Out     1.544     5.826 r     -         
un11_count_cry_2           Net         -        -       -         -           1         
U6.un11_count_cry_3_0      CCU2D       CIN      In      0.000     5.826 r     -         
U6.un11_count_cry_3_0      CCU2D       COUT     Out     0.143     5.969 r     -         
un11_count_cry_4           Net         -        -       -         -           1         
U6.un11_count_cry_5_0      CCU2D       CIN      In      0.000     5.969 r     -         
U6.un11_count_cry_5_0      CCU2D       COUT     Out     0.143     6.111 r     -         
un11_count_cry_6           Net         -        -       -         -           1         
U6.un11_count_cry_7_0      CCU2D       CIN      In      0.000     6.111 r     -         
U6.un11_count_cry_7_0      CCU2D       COUT     Out     0.143     6.254 r     -         
un11_count_cry_8           Net         -        -       -         -           1         
U6.un11_count_cry_9_0      CCU2D       CIN      In      0.000     6.254 r     -         
U6.un11_count_cry_9_0      CCU2D       COUT     Out     0.143     6.397 r     -         
un11_count_cry_10          Net         -        -       -         -           1         
U6.un11_count_cry_11_0     CCU2D       CIN      In      0.000     6.397 r     -         
U6.un11_count_cry_11_0     CCU2D       COUT     Out     0.143     6.540 r     -         
un11_count_cry_12          Net         -        -       -         -           1         
U6.un11_count_cry_13_0     CCU2D       CIN      In      0.000     6.540 r     -         
U6.un11_count_cry_13_0     CCU2D       COUT     Out     0.143     6.683 r     -         
un11_count_cry_14          Net         -        -       -         -           1         
U6.un11_count_cry_15_0     CCU2D       CIN      In      0.000     6.683 r     -         
U6.un11_count_cry_15_0     CCU2D       COUT     Out     0.143     6.825 r     -         
un11_count_cry_16          Net         -        -       -         -           1         
U6.un11_count_cry_17_0     CCU2D       CIN      In      0.000     6.825 r     -         
U6.un11_count_cry_17_0     CCU2D       COUT     Out     0.143     6.968 r     -         
un11_count_cry_18          Net         -        -       -         -           1         
U6.un11_count_cry_19_0     CCU2D       CIN      In      0.000     6.968 r     -         
U6.un11_count_cry_19_0     CCU2D       COUT     Out     0.143     7.111 r     -         
un11_count_cry_20          Net         -        -       -         -           1         
U6.un11_count_cry_21_0     CCU2D       CIN      In      0.000     7.111 r     -         
U6.un11_count_cry_21_0     CCU2D       COUT     Out     0.143     7.254 r     -         
un11_count_cry_22          Net         -        -       -         -           1         
U6.un11_count_cry_23_0     CCU2D       CIN      In      0.000     7.254 r     -         
U6.un11_count_cry_23_0     CCU2D       COUT     Out     0.143     7.397 r     -         
un11_count_cry_24          Net         -        -       -         -           1         
U6.un11_count_cry_25_0     CCU2D       CIN      In      0.000     7.397 r     -         
U6.un11_count_cry_25_0     CCU2D       COUT     Out     0.143     7.539 r     -         
un11_count_cry_26          Net         -        -       -         -           1         
U6.un11_count_cry_27_0     CCU2D       CIN      In      0.000     7.539 r     -         
U6.un11_count_cry_27_0     CCU2D       COUT     Out     0.143     7.682 r     -         
un11_count_cry_28          Net         -        -       -         -           1         
U6.un11_count_cry_29_0     CCU2D       CIN      In      0.000     7.682 r     -         
U6.un11_count_cry_29_0     CCU2D       COUT     Out     0.143     7.825 r     -         
un11_count_cry_30          Net         -        -       -         -           1         
U6.un11_count_cry_31_0     CCU2D       CIN      In      0.000     7.825 r     -         
U6.un11_count_cry_31_0     CCU2D       COUT     Out     0.143     7.968 r     -         
un11_count_cry_32          Net         -        -       -         -           1         
U6.un11_count_s_33_0       CCU2D       CIN      In      0.000     7.968 r     -         
U6.un11_count_s_33_0       CCU2D       S0       Out     1.549     9.517 r     -         
un11_count_s_33_0_S0_0     Net         -        -       -         -           1         
U6.count[15]               FD1S3IX     D        In      0.000     9.517 r     -         
========================================================================================




====================================
<a name=clockReport36></a>Detailed Report for Clock: Top|Clk_Count_derived_clock[13]</a>
====================================



<a name=startingSlack37></a>Starting Points with Worst Slack</a>
********************************

                Starting                                                                    Arrival           
Instance        Reference                           Type        Pin     Net                 Time        Slack 
                Clock                                                                                         
--------------------------------------------------------------------------------------------------------------
U2.Count[7]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       KEY_NonShake[1]     1.108       14.697
U1.Count[7]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       KEY_NonShake[0]     1.108       14.697
U2.Count[0]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[0]            0.972       15.401
U1.Count[0]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[0]            0.972       15.401
U2.Count[1]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[1]            0.972       15.543
U1.Count[1]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[1]            0.972       15.543
U2.Count[2]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[2]            0.972       15.543
U1.Count[2]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[2]            0.972       15.543
U2.Count[3]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[3]            0.972       15.686
U1.Count[3]     Top|Clk_Count_derived_clock[13]     FD1S3IX     Q       Count[3]            0.972       15.686
==============================================================================================================


<a name=endingSlack38></a>Ending Points with Worst Slack</a>
******************************

                Starting                                                                             Required           
Instance        Reference                           Type        Pin     Net                          Time         Slack 
                Clock                                                                                                   
------------------------------------------------------------------------------------------------------------------------
U2.Count[7]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_s_7_0_S0         19.894       14.697
U1.Count[7]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_s_7_0_S0_0       19.894       14.697
U2.Count[5]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_5_0_S0       19.894       14.839
U1.Count[5]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_5_0_S0_0     19.894       14.839
U2.Count[6]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_5_0_S1       19.894       14.839
U1.Count[6]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_5_0_S1_0     19.894       14.839
U2.Count[3]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_3_0_S0       19.894       14.982
U1.Count[3]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_3_0_S0_0     19.894       14.982
U2.Count[4]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_3_0_S1       19.894       14.982
U1.Count[4]     Top|Clk_Count_derived_clock[13]     FD1S3IX     D       un1_Count_1_cry_3_0_S1_0     19.894       14.982
========================================================================================================================



<a name=worstPaths39></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:88779:90753:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.894

    - Propagation time:                      5.198
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 14.697

    Number of logic level(s):                6
    Starting point:                          U2.Count[7] / Q
    Ending point:                            U2.Count[7] / D
    The start point is clocked by            Top|Clk_Count_derived_clock[13] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    The end   point is clocked by            Top|Clk_Count_derived_clock[13] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:Top|Clk_Count_derived_clock[13] to c:Top|Clk_Count_derived_clock[13])

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                           Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
U2.Count[7]                    FD1S3IX     Q        Out     1.108     1.108 r     -         
KEY_NonShake[1]                Net         -        -       -         -           3         
U2.un1_Count_1_cry_0_0_RNO     INV         A        In      0.000     1.108 r     -         
U2.un1_Count_1_cry_0_0_RNO     INV         Z        Out     0.568     1.676 f     -         
KEY_NonShake_i[1]              Net         -        -       -         -           1         
U2.un1_Count_1_cry_0_0         CCU2D       B0       In      0.000     1.676 f     -         
U2.un1_Count_1_cry_0_0         CCU2D       COUT     Out     1.544     3.220 r     -         
un1_Count_1_cry_0              Net         -        -       -         -           1         
U2.un1_Count_1_cry_1_0         CCU2D       CIN      In      0.000     3.220 r     -         
U2.un1_Count_1_cry_1_0         CCU2D       COUT     Out     0.143     3.363 r     -         
un1_Count_1_cry_2              Net         -        -       -         -           1         
U2.un1_Count_1_cry_3_0         CCU2D       CIN      In      0.000     3.363 r     -         
U2.un1_Count_1_cry_3_0         CCU2D       COUT     Out     0.143     3.506 r     -         
un1_Count_1_cry_4              Net         -        -       -         -           1         
U2.un1_Count_1_cry_5_0         CCU2D       CIN      In      0.000     3.506 r     -         
U2.un1_Count_1_cry_5_0         CCU2D       COUT     Out     0.143     3.649 r     -         
un1_Count_1_cry_6              Net         -        -       -         -           1         
U2.un1_Count_1_s_7_0           CCU2D       CIN      In      0.000     3.649 r     -         
U2.un1_Count_1_s_7_0           CCU2D       S0       Out     1.549     5.198 r     -         
un1_Count_1_s_7_0_S0           Net         -        -       -         -           1         
U2.Count[7]                    FD1S3IX     D        In      0.000     5.198 r     -         
============================================================================================




====================================
<a name=clockReport40></a>Detailed Report for Clock: Top|Clk_Count_derived_clock[16]</a>
====================================



<a name=startingSlack41></a>Starting Points with Worst Slack</a>
********************************

                   Starting                                                                   Arrival           
Instance           Reference                           Type        Pin     Net                Time        Slack 
                   Clock                                                                                        
----------------------------------------------------------------------------------------------------------------
TB_watchdog[8]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[8]     1.180       6.949 
TB_watchdog[0]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[0]     0.972       15.401
TB_watchdog[1]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[1]     0.972       15.543
TB_watchdog[2]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[2]     0.972       15.543
TB_watchdog[3]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[3]     0.972       15.686
TB_watchdog[4]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[4]     0.972       15.686
TB_watchdog[5]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[5]     0.972       15.829
TB_watchdog[6]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[6]     0.972       15.829
TB_watchdog[7]     Top|Clk_Count_derived_clock[16]     FD1P3DX     Q       TB_watchdog[7]     0.972       17.713
================================================================================================================


<a name=endingSlack42></a>Ending Points with Worst Slack</a>
******************************

                   Starting                                                                     Required           
Instance           Reference                           Type        Pin     Net                  Time         Slack 
                   Clock                                                                                           
-------------------------------------------------------------------------------------------------------------------
TB_watchdog[7]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[7]     19.894       15.401
TB_watchdog[8]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[8]     19.894       15.401
TB_watchdog[5]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[5]     19.894       15.543
TB_watchdog[6]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[6]     19.894       15.543
TB_watchdog[3]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[3]     19.894       15.686
TB_watchdog[4]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[4]     19.894       15.686
TB_watchdog[1]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[1]     19.894       15.829
TB_watchdog[2]     Top|Clk_Count_derived_clock[16]     FD1P3DX     D       TB_watchdog_s[2]     19.894       15.829
TB_watchdog[0]     Top|Clk_Count_derived_clock[16]     FD1P3DX     SP      TB_watchdoge         19.528       17.076
TB_watchdog[1]     Top|Clk_Count_derived_clock[16]     FD1P3DX     SP      TB_watchdoge         19.528       17.076
===================================================================================================================



<a name=worstPaths43></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:95650:96154:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      2.580
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 6.949

    Number of logic level(s):                1
    Starting point:                          TB_watchdog[8] / Q
    Ending point:                            U5.Delay_set[0] / SP
    The start point is clocked by            Top|Clk_Count_derived_clock[16] [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    The end   point is clocked by            Top|Clk [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
TB_watchdog[8]      FD1P3DX      Q        Out     1.180     1.180 r     -         
TB_watchdog[8]      Net          -        -       -         -           5         
TB_sig              ORCALUT4     C        In      0.000     1.180 r     -         
TB_sig              ORCALUT4     Z        Out     1.400     2.580 r     -         
PulseOut_c[0]       Net          -        -       -         -           51        
U5.Delay_set[0]     FD1P3AX      SP       In      0.000     2.580 r     -         
==================================================================================




====================================
<a name=clockReport44></a>Detailed Report for Clock: Top|FSMC_NADV</a>
====================================



<a name=startingSlack45></a>Starting Points with Worst Slack</a>
********************************

                Starting                                              Arrival          
Instance        Reference         Type        Pin     Net             Time        Slack
                Clock                                                                  
---------------------------------------------------------------------------------------
FSMC_Add[0]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[0]     1.305       3.385
FSMC_Add[1]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[1]     1.305       3.385
FSMC_Add[2]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[2]     1.305       3.385
FSMC_Add[3]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[3]     1.272       4.507
FSMC_Add[4]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[4]     1.044       8.428
FSMC_Add[5]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[5]     1.044       8.428
FSMC_Add[6]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[6]     1.044       8.428
FSMC_Add[7]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[7]     1.044       8.428
FSMC_Add[8]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[8]     1.044       8.428
FSMC_Add[9]     Top|FSMC_NADV     FD1S3AX     Q       FSMC_Add[9]     1.044       8.428
=======================================================================================


<a name=endingSlack46></a>Ending Points with Worst Slack</a>
******************************

                 Starting                                                 Required          
Instance         Reference         Type        Pin     Net                Time         Slack
                 Clock                                                                      
--------------------------------------------------------------------------------------------
FSMC_Add[10]     Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[10]     10.089       3.385
FSMC_Add[11]     Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[11]     10.089       3.385
FSMC_Add[13]     Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[13]     10.089       3.385
FSMC_Add[14]     Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[14]     10.089       3.385
FSMC_Add[0]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[0]      10.089       3.457
FSMC_Add[1]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[1]      10.089       3.457
FSMC_Add[2]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[2]      10.089       3.457
FSMC_Add[3]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[3]      10.089       3.457
FSMC_Add[4]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[4]      10.089       3.457
FSMC_Add[5]      Top|FSMC_NADV     FD1S3AX     D       FSMC_Add_0[5]      10.089       3.457
============================================================================================



<a name=worstPaths47></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:100412:101732:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.089

    - Propagation time:                      6.704
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.385

    Number of logic level(s):                4
    Starting point:                          FSMC_Add[0] / Q
    Ending point:                            FSMC_Add[11] / D
    The start point is clocked by            Top|FSMC_NADV [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
    The end   point is clocked by            Top|FSMC_NADV [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                    Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
FSMC_Add[0]             FD1S3AX      Q        Out     1.305     1.305 r     -         
FSMC_Add[0]             Net          -        -       -         -           27        
un21_fsmc_ad[11]        ORCALUT4     A        In      0.000     1.305 r     -         
un21_fsmc_ad[11]        ORCALUT4     Z        Out     1.089     2.394 r     -         
N_558                   Net          -        -       -         -           2         
FSMC_AD_pad_RNO[11]     ORCALUT4     B        In      0.000     2.394 r     -         
FSMC_AD_pad_RNO[11]     ORCALUT4     Z        Out     1.017     3.411 r     -         
FSMC_AD_pad_RNO[11]     Net          -        -       -         -           1         
FSMC_AD_pad[11]         BB           I        In      0.000     3.411 r     -         
FSMC_AD_pad[11]         BB           O        Out     2.676     6.087 r     -         
FSMC_AD_in[11]          Net          -        -       -         -           9         
FSMC_Add_0[11]          ORCALUT4     A        In      0.000     6.087 r     -         
FSMC_Add_0[11]          ORCALUT4     Z        Out     0.617     6.704 r     -         
FSMC_Add_0[11]          Net          -        -       -         -           1         
FSMC_Add[11]            FD1S3AX      D        In      0.000     6.704 r     -         
======================================================================================




====================================
<a name=clockReport48></a>Detailed Report for Clock: Top|FSMC_NWE</a>
====================================



<a name=startingSlack49></a>Starting Points with Worst Slack</a>
********************************

                     Starting                                               Arrival          
Instance             Reference        Type         Pin     Net              Time        Slack
                     Clock                                                                   
---------------------------------------------------------------------------------------------
reg_mem_0_0io[0]     Top|FSMC_NWE     IFS1P3DX     Q       reg_mem_0[0]     1.220       3.965
reg_mem_0_0io[2]     Top|FSMC_NWE     IFS1P3DX     Q       Cross_EN_c       1.044       4.141
reg_mem_5[0]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[0]     0.972       4.168
reg_mem_5[1]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[1]     0.972       4.310
reg_mem_5[2]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[2]     0.972       4.310
reg_mem_5[3]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[3]     0.972       4.453
reg_mem_5[4]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[4]     0.972       4.453
reg_mem_5[5]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[5]     0.972       4.596
reg_mem_5[6]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[6]     0.972       4.596
reg_mem_5[7]         Top|FSMC_NWE     FD1P3AX      Q       reg_mem_5[7]     0.972       4.739
=============================================================================================


<a name=endingSlack50></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                Required          
Instance             Reference        Type         Pin     Net               Time         Slack
                     Clock                                                                     
-----------------------------------------------------------------------------------------------
reg_mem_0_0io[8]     Top|FSMC_NWE     IFS1P3DX     D       FSMC_AD_in[8]     9.894        3.965
reg_mem_1[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_3[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_4[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_5[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_6[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_7[8]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[8]     9.894        3.965
reg_mem_ram_1        Top|FSMC_NWE     SPR16X4C     DI0     FSMC_AD_in[8]     10.000       4.070
reg_mem_0_0io[9]     Top|FSMC_NWE     IFS1P3DX     D       FSMC_AD_in[9]     9.894        4.141
reg_mem_1[9]         Top|FSMC_NWE     FD1P3AX      D       FSMC_AD_in[9]     9.894        4.141
===============================================================================================



<a name=worstPaths51></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:106134:107178:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      5.930
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.965

    Number of logic level(s):                3
    Starting point:                          reg_mem_0_0io[0] / Q
    Ending point:                            reg_mem_0_0io[8] / D
    The start point is clocked by            Top|FSMC_NWE [rising] (rise=0.000 fall=5.000 period=10.000) on pin SCLK
    The end   point is clocked by            Top|FSMC_NWE [rising] (rise=0.000 fall=5.000 period=10.000) on pin SCLK

Instance / Net                      Pin      Pin               Arrival     No. of    
Name                   Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------
reg_mem_0_0io[0]       IFS1P3DX     Q        Out     1.220     1.220 r     -         
reg_mem_0[0]           Net          -        -       -         -           8         
un21_fsmc_ad[8]        ORCALUT4     D        In      0.000     1.220 r     -         
un21_fsmc_ad[8]        ORCALUT4     Z        Out     1.017     2.237 r     -         
N_555                  Net          -        -       -         -           1         
FSMC_AD_pad_RNO[8]     ORCALUT4     B        In      0.000     2.237 r     -         
FSMC_AD_pad_RNO[8]     ORCALUT4     Z        Out     1.017     3.253 r     -         
FSMC_AD_pad_RNO[8]     Net          -        -       -         -           1         
FSMC_AD_pad[8]         BB           I        In      0.000     3.253 r     -         
FSMC_AD_pad[8]         BB           O        Out     2.676     5.930 r     -         
FSMC_AD_in[8]          Net          -        -       -         -           9         
reg_mem_0_0io[8]       IFS1P3DX     D        In      0.000     5.930 r     -         
=====================================================================================




====================================
<a name=clockReport52></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack53></a>Starting Points with Worst Slack</a>
********************************

                   Starting                                             Arrival          
Instance           Reference     Type        Pin     Net                Time        Slack
                   Clock                                                                 
-----------------------------------------------------------------------------------------
SPulseCount[0]     System        FD1P3DX     Q       SPulseCount[0]     1.044       4.096
SPulseCount[1]     System        FD1P3DX     Q       SPulseCount[1]     1.044       4.238
SPulseCount[2]     System        FD1P3DX     Q       SPulseCount[2]     1.044       4.238
SPulseCount[3]     System        FD1P3DX     Q       SPulseCount[3]     1.044       4.381
SPulseCount[4]     System        FD1P3DX     Q       SPulseCount[4]     1.044       4.381
SPulseCount[5]     System        FD1P3DX     Q       SPulseCount[5]     1.044       4.524
SPulseCount[6]     System        FD1P3DX     Q       SPulseCount[6]     1.044       4.524
SPulseCount[7]     System        FD1P3DX     Q       SPulseCount[7]     1.044       4.667
SPulseCount[8]     System        FD1P3DX     Q       SPulseCount[8]     1.044       4.667
SPulseCount[9]     System        FD1P3DX     Q       SPulseCount[9]     1.044       4.809
=========================================================================================


<a name=endingSlack54></a>Ending Points with Worst Slack</a>
******************************

                   Starting                                          Required          
Instance           Reference     Type        Pin     Net             Time         Slack
                   Clock                                                               
---------------------------------------------------------------------------------------
SPulseCount[0]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[1]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[2]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[3]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[4]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[5]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[6]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[7]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[8]     System        FD1P3DX     SP      spulsecount     9.528        4.096
SPulseCount[9]     System        FD1P3DX     SP      spulsecount     9.528        4.096
=======================================================================================



<a name=worstPaths55></a>Worst Path Information</a>
<a href="D:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srr:srsfD:\Light_Source\CPLD\CL202_B(I232O232-202107231608)\MXO2_2000HC\CL202_MXO2_2000HC.srs:fp:111406:114046:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         9.528

    - Propagation time:                      5.433
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 4.095

    Number of logic level(s):                9
    Starting point:                          SPulseCount[0] / Q
    Ending point:                            SPulseCount[0] / SP
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            System [rising] on pin CK

Instance / Net                       Pin      Pin               Arrival     No. of    
Name                     Type        Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------
SPulseCount[0]           FD1P3DX     Q        Out     1.044     1.044 r     -         
SPulseCount[0]           Net         -        -       -         -           2         
spulsecount_cry_0_0      CCU2D       B1       In      0.000     1.044 r     -         
spulsecount_cry_0_0      CCU2D       COUT     Out     1.544     2.588 r     -         
spulsecount_cry_0        Net         -        -       -         -           1         
spulsecount_cry_1_0      CCU2D       CIN      In      0.000     2.588 r     -         
spulsecount_cry_1_0      CCU2D       COUT     Out     0.143     2.731 r     -         
spulsecount_cry_2        Net         -        -       -         -           1         
spulsecount_cry_3_0      CCU2D       CIN      In      0.000     2.731 r     -         
spulsecount_cry_3_0      CCU2D       COUT     Out     0.143     2.874 r     -         
spulsecount_cry_4        Net         -        -       -         -           1         
spulsecount_cry_5_0      CCU2D       CIN      In      0.000     2.874 r     -         
spulsecount_cry_5_0      CCU2D       COUT     Out     0.143     3.017 r     -         
spulsecount_cry_6        Net         -        -       -         -           1         
spulsecount_cry_7_0      CCU2D       CIN      In      0.000     3.017 r     -         
spulsecount_cry_7_0      CCU2D       COUT     Out     0.143     3.159 r     -         
spulsecount_cry_8        Net         -        -       -         -           1         
spulsecount_cry_9_0      CCU2D       CIN      In      0.000     3.159 r     -         
spulsecount_cry_9_0      CCU2D       COUT     Out     0.143     3.302 r     -         
spulsecount_cry_10       Net         -        -       -         -           1         
spulsecount_cry_11_0     CCU2D       CIN      In      0.000     3.302 r     -         
spulsecount_cry_11_0     CCU2D       COUT     Out     0.143     3.445 r     -         
spulsecount_cry_12       Net         -        -       -         -           1         
spulsecount_cry_13_0     CCU2D       CIN      In      0.000     3.445 r     -         
spulsecount_cry_13_0     CCU2D       COUT     Out     0.143     3.588 r     -         
spulsecount_cry_14       Net         -        -       -         -           1         
spulsecount_cry_15_0     CCU2D       CIN      In      0.000     3.588 r     -         
spulsecount_cry_15_0     CCU2D       S1       Out     1.845     5.433 r     -         
spulsecount              Net         -        -       -         -           17        
SPulseCount[0]           FD1P3DX     SP       In      0.000     5.433 r     -         
======================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 273MB peak: 274MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 273MB peak: 274MB)

---------------------------------------
<a name=resourceUsage56></a>Resource Usage Report</a>
Part: lcmxo2_2000he-4

Register bits: 433 of 2112 (21%)
Latch bits:      1
PIC Latch:       0
I/O cells:       53


Details:
BB:             16
CCU2D:          252
FD1P3AX:        209
FD1P3DX:        50
FD1P3IX:        4
FD1S1D:         1
FD1S3AX:        37
FD1S3DX:        2
FD1S3IX:        114
GSR:            1
IB:             17
IFS1P3DX:       16
INV:            19
OB:             20
OFS1P3IX:       1
ORCALUT4:       103
PUR:            1
SPR16X4C:       4
VHI:            9
VLO:            9
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 274MB)

Process took 0h:00m:03s realtime, 0h:00m:01s cputime
# Tue Nov 19 16:15:04 2024

###########################################################]

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